Field effect transistors such as MOSFETs fabricated in silicon-on-insulator (SOI) substrates may be susceptible to relatively low source-to-drain breakdown voltages due to floating body effects. In addition, excess holes in nMOSFETs may be generated by impact ionization and may accumulate near the source/body junction therein. A sufficient number of holes may accumulate and forward bias the body with respect to the source and thereby lower the threshold voltage of the MOSFET through the body-bias effect. Furthermore, a "kick" effect in the I-V characteristics may be present because of additional current flow.
Attempts have been made to utilize low barrier body contacts underneath the source region of an SOI transistor to collect current generated by impact ionization. One such attempt is disclosed in U.S. Pat. No. 5,489,792 to Hu. et al. entitled "Silicon-On-Insulator Transistors Having Improved Current Characteristics and Reduced Electrostatic Discharge Susceptibility". In particular, the '792 patent discloses an SOI MOSFET having a P-type channel region and a low barrier P-type body contact region 18 between an N+ source region 16 and a buried silicon dioxide layer 12. Here, the low barrier P-type body contact region 18 forms a P-N junction with the N+ source region 16. Because this P-N junction inhibits conduction directly through the source region, a P+ side contact 20 is formed to provide a current path for impact ionization current. Unfortunately, the inclusion of this P+ side contact 20 increases the unit cell size of an SOI MOSFET and complicates the fabrication process.
Thus, notwithstanding the above-described SOI MOSFET, there continues to be a need for improved SOI-based transistors having reduced susceptibility to parasitic floating body effects and methods of forming same.